As the integrated circuit technology advances towards large-scale integration and high performance circuits, it becomes necessary to provide interconnection electrical packaging which is compatible with the performance demands of the associated circuitry. In efforts to achieve more complex (e.g. dense) circuits, one approach has been to use multi-level glass-ceramic or ceramic microelectronic structure, which comprise composite dielectric bodies having electrically connected conductive patterns that may exist at a plurality of distinct horizontal levels.
A common method for fabricating such multi-level dielectric structures involves formulating ceramic or glass-ceramic particles into a paint with binder and solvent; forming the paint into a slip with conversion by evaporation of the solvent into a flexible sheet of required size, referred to as a green sheet; forming terminal holes and via holes as predetermined locations in separate sheets; depositing electrode paste on desired areas of the separate sheets once in the via holes; stacking or superimposing the sheets one on the other in required registration; and firing the stacked sheets to burn out the binder and to sinter the dielectric particles and to convert the paste into conductors, which results in a monolithic structure. At an appropriate point in the fabrication process, contact pins are embedded in the terminal holes for establishing an electrical path from these conductors to external circuitry. More extensive details as to such fabrication process can be found in U.S. Pat. No. 3,518,756 and No. 3,988,405, as well as in the article "A Fabrication Technique For Multi-Layer Ceramic Modules" by H. D. Kaiser et al., Solid State Technology, May 1972, pp. 35-40 and in the article "The Third Dimension in Thick-Films Multilayer Technology" by W. L. Clough, Microelectronics, Vol. 13, No. 9 (1970), pp. 23-30.
Although the foregoing technique has found extensive acceptance in the art, it is nevertheless characterized with limitations with continuing increase in the densities of integrated circuits. This situation requires increased complexity of the internal metallurgical patterns embedded in the multi-layer dielectric substrate or module with respect to the number of conductor layers required, together with the number of interconnecting via holes and associated increased number of terminal pads required for electrical connection to the corresponding increased number of contact points on the active surface of an integrated circuit device. Also, such structures are characterized with via bulges which detract from the planarity of the structure.